VESD05A8B-HNH document number 81741 rev. 1.2, 11-jun-10 vishay semiconductors www.vishay.com 1 20522 1 2 3 4 8 7 6 5 20521 9 for technical support, please contact: esdprotection@vishay.com 8-line esd-protection diode array in llp1713-9l features ? ultra compact llp1713-9l package ? low package profile < 0.6 mm ? 8-line esd-protection ? low leakage current i r < 0.5 a ? low load capacitance c d = 20 pf ? esd-immunity acc. iec 61000-4-2 17 kv contact discharge 17 kv air discharge ? working voltage range v rwm = 5 v ? e4 - precious metal (e .g. ag, au, nipd, nipdau) (no sn) ? compliant to rohs directive 2002/95/ec and in accordance to weee 2002/96/ec marking (example only) dot = pin 1 marking y = type code (see table below) xx = date code ordering information package data ** please see document ?vishay material category policy? www.vishay.com/doc?99902 yxx 20719 device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity VESD05A8B-HNH VESD05A8B-HNH-gs08 3000 15 000 device name package name marking code weight molding compound flammability rating moisture sensitivity level soldering conditions VESD05A8B-HNH llp1713-9l e 3.7 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals
www.vishay.com 2 document number 81741 rev. 1.2, 11-jun-10 VESD05A8B-HNH vishay semiconductors for technical support, please contact: esdprotection@vishay.com absolute maximum ratings bias -mode (8-line bi directional as ymmetrical protection mode) with the VESD05A8B-HNH up to 8 signal- or data-lines (l1 - l8) can be protected against voltage transients. with pin 9 connected to ground and pin 1 up to pin 8 connected to a signal- or data-line which has to be pro- tected. as long as the voltage level on the data- or signal-line is between 0 v (ground level) and the specified m aximum r everse w orking v oltage ( v rwm ) the protection diode between data line and ground offer a high isolation to the ground line. the protection device behaves like an open switch. as soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the tr ansient current to ground. now the protection device behaves like a closed switch. the c lamping v oltage ( v c ) is defined by the br eakthrough v oltage ( v br ) level plus the voltage drop at the series impedance (res istance and inductance) of the protection device. any negative transient signal will be cl amped accordingly. the ne gative transient current is flowing in the for- ward direction of the protection diode. the low f orward v oltage ( v f ) clamps the negative transient close to the ground level. due to the different clamping levels in forward and reverse direction the VESD05A8B-HNH clamping behaviour is bi directional and as ymmetrical ( bias ). rating test conditions symbol value unit peak pulse current bias-mode: each input (pin 1 - pin 8) to ground (pin 9); acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 4a bisy-mode: each input (pin 1 - pin 8) to any other input pin. pin 9 not connected. acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 3a peak pulse power bias-mode: each input (pin 1 - pin 8) to ground (pin 9); acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 52 w bisy-mode: each input (pin 1 - pin 8) to any other input pin. pin 9 not connected. acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 45 w esd-immunity acc. iec61000-4-2; 10 pulses bias-mode: each input (pin 1 - pin 8) to ground (pin 9) contact discharge v esd 17 kv air discharge v esd 17 kv acc. iec 61000-4-2 ; 10 pulses bisy-mode: each input (pin 1 - pin 8) to any other input pin. pin 9 not connected contact discharge v esd 10 kv air discharge v esd 10 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t stg - 55 to + 150 c l1 l 8 l3 l6 l2 l7 l4 l5 20524 1 2 3 4 8 7 6 5 9
VESD05A8B-HNH document number 81741 rev. 1.2, 11-jun-10 vishay semiconductors www.vishay.com 3 for technical support, please contact: esdprotection@vishay.com electrical characteristics ratings at 25 c, ambient temperature unless otherwise specified VESD05A8B-HNH bias mode: each input (pin 1 - pin 8) to ground (pin 9) if a higher surge current or p eak p ulse current ( i pp ) is needed, some protection diodes in the VESD05A8B-HNH can also be used in parallel in order to "multiply" the performance. if two diodes are switched in parallel you get ? double surge power = double peak pulse current (2 x i ppm ) ? half of the line inductance = reduced clamping voltage ? half of the line resistance = reduced clamping voltage ? double line c apacitance (2 x c d ) ? double r everse leakage current (2 x i r ) parameter test conditions/remarks symbol min. ty p. max. unit protection paths number of line wh ich can be protected n lines 8 lines reverse current at i r = 0.5 a v rwm 5v max. reverse current at v r = v rwm = 5 v i r 0.5 a min. reverse breakdown voltage at i r = 1 ma v br 68v max. clamping voltage at i pp = 4 a acc. iec 61000-4-5 v c 13 v max. forward clamping voltage at i f = 4 a acc. iec 61000-4-5 v f 4.5 v line capacitance at v r = 0 v; f = 1 mhz c d 20 23 pf at v r = 2.5 v; f = 1 mhz c d 12 14 pf l1 l4 l2 l3 20525 1 2 3 4 8 7 6 5 9
www.vishay.com 4 document number 81741 rev. 1.2, 11-jun-10 VESD05A8B-HNH vishay semiconductors for technical support, please contact: esdprotection@vishay.com bisy -mode (7-line bi directional sy mmetrical protection mode) if a bipolar symmetrical protection device is needed the VESD05A8B-HNH can also be used as a seven-line protection device. therefore seven pins (example: pin 1, 2, 3, 4, 6, 7 and 8) has to be connected to the signal- or data-line (l1 - l7) and pin 5 to ground. pin 9 must not be connected! positive and negative volt age transients will be clamped in the same way. the clam ping current from one data line through the VESD05A8B-HNH to the ground passes one diode in forward direction and the other one in reverse direction. the c lamping v oltage ( v c ) is defined by the br eakthrough v oltage ( v br ) level of one diode plus the forward voltage of the other diode plus the vo ltage drop at the series impedances (resistances and inductances) of the protection device. due to the same clamping levels in positive and negative direction the VESD05A8B-HNH voltage clamping behaviour is also bi directional and sy mmetrical ( bisy ). electrical characteristics ratings at 25 c, ambient temperature unless otherwise specified VESD05A8B-HNH bisy mode: each input (pin 1 - pin 8) to any othe r input pin connected to ground; pin 9 not connected parameter test conditions/remarks symbol min. ty p. max. unit protection paths number of line which can be protected n lines 7lines reverse current at i r = 0.5 a v rwm 5.5 v max. reverse current at v r = v rwm = 5.5 v i r 0.5 a min. reverse breakdown voltage at i r = 1 ma v br 6.5 8.7 v max. clamping voltage at i pp = 3 a acc. iec 61000-4-5 v c 15 v line capacitance at v r = 0 v; f = 1 mhz c d 10 13 pf at v r = 2.5 v; f = 1 mhz c d 810pf l1 l7 l3 l5 l2 l6 l4 20526_1 1 2 3 4 8 7 6 5 9
VESD05A8B-HNH document number 81741 rev. 1.2, 11-jun-10 vishay semiconductors www.vishay.com 5 for technical support, please contact: esdprotection@vishay.com typical characteristics t amb = 25 c, unless otherwise specified figure 1. 8/20 s peak pulse current wave form acc. iec 61000-4-5 figure 2. esd discharge current wave form acc. iec 61000-4-2 (330 ? /150 pf) figure 3. typical capacitance c d vs. reverse voltage v r 0 % 20 % 40 % 60 % 8 0 % 100 % 010203040 time ( s) i ppm 20 s to 50 % 8 s to 100 % 2054 8 0 % 20 % 40 % 60 % 8 0 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 8 0 90 100 time (ns) discharge c u rrent i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 5 10 15 20 25 0123456 f = 1 mhz bias-mode bisy-mode pin 1, 2, 3, 4, 5, 6, 7 or 8 to pin 9 b et w een t w o pins (1 - 8 ) pin 9 not connetced v r ( v ) c d (pf) 2077 8 figure 4. typical forward current i f vs. forward voltage v f figure 5. typical reverse voltage v r vs. reverse current i r figure 6. typical peak clamping voltage v c vs. peak pulse current i pp 0.001 0.01 0.1 1 10 100 0.5 0.6 0.7 0. 8 0.9 1 v f ( v ) i f (ma) 207 8 0 pin 9 to pin 1, 2, 3, 4, 5, 6, 7 or 8 0 1 2 3 4 5 6 7 8 0.01 0.1 1 10 100 1000 10000 pin 1, 2, 3, 4, 5, 6, 7 or 8 to pin 9 i r ( a) v r ( v ) 207 8 1 - 4 - 2 0 2 4 6 8 10 012345 v c positi v e s u rge negati v e s u rge meas u red acc. iec 61000-4-5 ( 8 /20 s - w a v e form) i pp (a) v c ( v ) 20779 14 12 pin 1, 2, 3, 4, 5, 6, 7 or 8 to pin 9
www.vishay.com 6 document number 81741 rev. 1.2, 11-jun-10 VESD05A8B-HNH vishay semiconductors for technical support, please contact: esdprotection@vishay.com package dimensions in millimeters (inches): llp1713-9l 203 8 6 foot print recommendation: created - date: 2 8 . a u g u st 2006 doc u ment no.:s 8 - v -3906.04-001 (4) 1.75 (0.069) 1.65 (0.065) pin 1 marking 0.05 (0.002) 0 (0.000) 0.152 (0.006) ref. 1.2 (0.047) ref. 0.3 (0.012) 0.24 (0.009) 0.4 (0.016) b sc 0.23 (0.009) 0.17 (0.007) 1.05 (0.041) 1.4 (0.055) 1.3 (0.051) 0.6 (0.024) 0.5 (0.020) 0.45 (0.01 8 ) 0.35 (0.014) exp. dap 0.2 (0.00 8 ) x 45 solder resist mask solder pad 0.4 (0.016) 0.2 (0.00 8 ) 3 x 0.4 = 1.2 (0.047) 1 (0.039) 0.4 (0.016) 0.15 (0.006) 0.4 (0.016) 0.42 (0.017) re v . 1 - date: 27. may 200 8
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